System-in-package (SIP) is an integration approach that is often utilized to achieve intelligent partitioning of the key components of an electronics system to achieve increased functionality using smaller form factors. One implementation of SIP technology applies three-dimensional integration, whereby one or more semiconductor die are stacked on top of a package substrate so as to increase the amount of circuitry that may exist per unit area.
Die stacking involves a process whereby a base die, such as a field programmable gate array (FPGA) for example, is attached to a package substrate to form a device package. The base die may also provide a platform for one or more stacked die, such as random access memory (RAM) or a microprocessor. Interconnections between the base die, the package substrate, and the one or more stacked die may be implemented using a plurality of implementations, such as using micro-bumps, solder bumps, solder balls, wire bonds, build-up vias, plated-through holes (PTHs), and associated through die vias (TDVs).
The inter-die signal path connections may be facilitated through the use of programmable heterogeneous integration (PHI) tiles. In general, a PHI tile consists of programmable multiplexers, TDVs, level translation circuits, test circuits, and dedicated power supply ports. A PHI tile is used to interconnect a base die having specific patterns of TDVs and associated input/output (I/O) pads with one or more stacked die having I/O pads that match the I/O pad placements of the base die. Logic signals existing within the stacked die may then be propagated to the base die using the associated TDVs, I/O pads, and level translation circuitry as may be required in a particular application.
Inter-die signal path connections may also be formed between the base die, the stacked die, and the package substrate to supply the one or more die with operational power. In particular, the package substrate may act as a power distribution system that may be comprised of multiple conductive layers, whereby pairs of conductive layers are arranged as power/ground plane pairs. Each power/ground plane pair of the package substrate is separated by a dielectric material, which acts as an insulative layer between the power/ground plane pair.
Turning to FIG. 1, a cross-section of exemplary die package 100 is shown, whereby one or more flip-chip die 106 may be coupled to package substrate 104 using, e.g., solder bump interconnection. In particular, the active side of die 106 contains an array of pads upon which solder bumps 110 are attached. Package substrate 104 similarly contains a corresponding array of pads, which electrically combine with solder bumps 110 to form the interconnection between die 106 and package substrate 104. Package substrate 104 also contains an array of pads upon which solder balls 108 are attached, so as to accommodate the interconnect between package substrate 104 and circuit board 102.
Power planes 120,122 and 116,118 may exist within the core of package substrate 104, or conversely, may exist within the build-up layers of package substrate 104, as power plane pairs. In particular, power plane 122 may provide a reference potential, e.g., ground potential, and power plane 120 may provide an operational potential that is referenced to the potential of ground plane 122. Similarly, power plane 118 may provide a reference potential, e.g., ground potential, and power plane 116 may provide an operational potential that is referenced to the potential of ground plane 118. Each operational and reference potential is then provided to die 106, via circuit board 102, using a plurality of plated-through holes (PTHs) that are implemented within the core of package substrate 104, combined with build-up vias, or laser vias, that are implemented within the build-up layers of package substrate 104.
Power planes 116-122 may comprise an entire conductive layer within the core of package substrate 104, or conversely, may be implemented as isolated “islands” of conductivity. In either instance, a characteristic impedance, Z0, is associated with each power plane pair and associated interconnect that provides operational power to die 106 from circuit board 102. Assuming the power planes and interconnects are lossless, the characteristic impedance of the power distribution system may be defined as:
                              Z          0                =                                            L              C                        ,                                              (        1        )            where L is the spreading inductance and C is the distributed capacitance of a particular power plane pair and associated interconnect. While the power distribution system is assumed to be lossless for purposes of analysis, typical power distribution systems often exhibit lossy characteristics, so as to dampen, or dissipate, resonance energy that may be created during high speed switching operations within die 106.
As can be verified from equation (1), minimization of the characteristic impedance of the power distribution system may be accomplished by: decreasing the spreading inductance L; increasing the distributed capacitance C; or a combination of both. The magnitude of spreading inductance exhibited by a power plane pair within a package substrate is directly proportional to the thickness of the dielectric layer that separates the operational power plane from the reference power plane. Thus, the spreading inductance increases as the thickness of the dielectric layer increases.
The distributed capacitance magnitude, on the other hand, is inversely proportional to the thickness of the dielectric layer that separates the operational power plane from the reference power plane. Thus, the distributed capacitance decreases as the thickness of the dielectric layer increases. It can be seen, therefore, that by decreasing the thickness of the dielectric layer, the spreading inductance may be decreased and the distributed capacitance may be increased, which decreases the overall impedance of the power distribution system in accordance with equation (1).
Conventional power distribution systems, however, utilize power plane pairs that are separated by dielectric layers having thicknesses between 35 μm and 100 μm. As such, the spreading inductance of the power plane pair is increased above a desirable limit and the distributed capacitance of the power plane pair is decreased below a desirable limit, which increases the overall impedance of the power distribution system beyond desirable limits.
Turning to FIG. 2, for example, a cross-section of conventional 3+4+3 power distribution system 200 is illustrated. The “3+4+3” convention used in the illustrated power distribution system of FIG. 2 denotes that 3 conductive layers are utilized within build-up portion 224, 4 conductive layers are utilized within core portion 228, and 3 conductive layers are utilized within build-up portion 226 of package substrate 204. Conductive layers within build-up portions 224 and 226 are interconnected using build-up vias 230 and 234, which are also known as laser vias. Build-up vias 230 and 234 may be offset from one another as illustrated, or conversely, may be aligned vertically to create stacked, build-up vias that exhibit similar effects of a plated-through hole due to their alignment in the X-Y plane. Interconnections within core portion 228 are generally implemented using PTHs 232, whereby PTHs 232 may be isolated from a particular conductive plane within core portion 228, or conversely, may be electrically coupled to a particular conductive plane within core portion 228.
Generally, power plane pairs 212,214 and 216,218 exist within core portion 228 to implement a power distribution system for die 206. In particular, package substrate 204 provides power plane pairs 212,214 and 216,218, which may be separated by a dielectric layer having thickness 220 and 222, respectively. The spreading inductance exhibited by power plane pairs 212,214 and 216,218 having a dielectric layer thickness of 35 μm, for example, is approximately equal to 45 pico henries per square. The distributed capacitance of such an arrangement is approximately equal to 112 pF/cm2. A 100 μm dielectric layer displaced between the power plane pairs, on the other hand, exhibits approximately 130 pico henries per square of spreading inductance and approximately 35 pF/cm2 of distributed capacitance.
Maximization of the distributed capacitance allows the power distribution system to maximize the ability to respond to dynamic current demands that are imposed by die 206. Similarly, minimization of the spreading inductance minimizes the reluctance of the power distribution system to retard changes in current flow. As discussed above, however, conventional power plane pairs exhibit relatively thicker dielectric layers, which increases the overall impedance of the power distribution system, thereby limiting the power distribution system's performance during dynamic current demands imposed by die 206. Given that additional die are stacked upon die 206 to form a stacked die package, the dynamic current demands that are imposed upon the power distribution system are even greater.
What is needed, therefore, is a power distribution system that both maximizes the distributed capacitances and minimizes the spreading inductance so as to optimize current flow for enhanced noise performance of a package substrate within, for example, a SIP based integration.